Scaling of Vertical InAs–GaSb Nanowire Tunneling Field-Effect Transistors on Si

Abstract

We demonstrate improved performance due to enhanced electrostatic control achieved by diameter scaling and gate placement in vertical InAs-GaSb tunneling field-effect transistors integrated on Si substrates. The best subthreshold swing, 68 mV/decade at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.3 V, was achieved for a device with 20-nm InAs diameter. The ON-current for the same device was 35 μA/μm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = 0.5 V and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.5 V. The fabrication technique used allow downscaling of the InAs diameter down to 11 nm with a flexible gate placement.