Improving GaN on Si Power Amplifiers through reduction of parasitic conduction layer

Abstract

This paper presents the influence of a doped Si region during the epi growth process on the performance of GaN on Si Power Amplifiers with significant improvement in GaN on Si performance achieved by reducing the doped Si region. Through load-pull and waveform measurements of a PCM GaN on Si device the impact of the doped region below the AlGaN buffer, termed the parasitic conduction layer, on PA performance is shown. By extracting a resistance value for the parasitic conduction layer a relationship between the achievable efficiency and parasitic conduction layer is developed and through further processing of the GaN on Si wafers to remove the doped Si layer this relationship proven. Enhancements in epi growth techniques to reduce the parasitic conduction layer are shown to improve the efficiency performance of the GaN on Si PA by over 7% on a 2mm device. The efficiency of a packaged 55W GaN on Si transistor also improved by over 5% from previous GaN on Si technology.