9.4 A 2×2 WLAN and Bluetooth combo SoC in 28nm CMOS with on-chip WLAN digital power amplifier, integrated 2G/BT SP3T switch and BT pulling cancelation

Abstract

The 2×2 wireless LAN (WLAN) + Bluetooth (BT) combo chip continues to be the most versatile product category in the wireless connectivity space. It finds usage in a wide range of applications, such as laptops, tablets, high-end smartphones, gaming consoles, set-top boxes, wireless routers and in-car/personal hot-spot devices. Digital-intensive SoCs have been relying on Moore's law to keep the cost down. However, traditional RF and analog circuits are facing more difficulties to keep up with Moore's law due to the physical constraint of inductors, capacitors, and resistors. To overcome these difficulties, we leveraged digital and mixed-signal techniques to architect the transceiver, with a WLAN Digital PA (DPA), a WLAN All-Digital PLL (ADPLL), a BT ADPLL with pulling cancellation, and a high-speed SAR-ADC with reduced analog filter order in the WLAN RX.