9.4 A 28nm CMOS digital fractional-N PLL with −245.5dB FOM and a frequency tripler for 802.11abgn/ac radio

Abstract

The fast adaptation of WiFi 802.11ac 256-QAM mode requires RF clocks with very low integrated phase error to deliver good EVM performance. On the other hand, smaller area and lower power are always desired for lower cost and longer battery life. This work presents a 28nm CMOS LO design for dual-band 802.11abgn/ac radio with overall architecture shown in Fig. 9.4.1. It addresses the aforementioned challenges with a low-noise integrated XTAL oscillator, a fractional-N digital PLL utilizing 1) background reference clock-doubler duty-cycle error correction and quantization noise cancellation, 2) non-periodic DCO dithering and compensation, and an offset LO frequency plan based on a self-mixing frequency tripler. The PLL design achieves 0.36° integrated phase error or 0.17ps rms jitter while consuming 9.5mW, leading to a record FOM of −245.5dBforfrac-N PLLs.