AlGaN/GaN MOS-HEMT With $\hbox{HfO}_{2}$ Dielectric and $\hbox{Al}_{2}\hbox{O}_{3}$ Interfacial Passivation Layer Grown by Atomic Layer Deposition

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> We have developed a novel AlGaN/GaN metal–oxide–semiconductor high-electron mobility transistor using a stack gate <formula formulatype="inline"><tex Notation="TeX">$\hbox{HfO}_{2}/\hbox{Al}_{2}\hbox{O}_{3}$</tex></formula> structure grown by atomic layer deposition. The stack gate consists of a thin <formula formulatype="inline"><tex Notation="TeX">$ \hbox{HfO}_{2}$</tex></formula> (30-<formula formulatype="inline"><tex Notation="TeX">$\hbox{\rm{\AA}}$</tex></formula>) gate dielectric and a thin <formula formulatype="inline"><tex Notation="TeX">$\hbox{Al}_{2}\hbox{O}_{3}$</tex></formula> (20- <formula formulatype="inline"><tex Notation="TeX">$\hbox{\rm{\AA}}$</tex></formula>) interfacial passivation layer (IPL). For the 50-<formula formulatype="inline"><tex Notation="TeX">$\hbox{\rm{\AA}}$</tex></formula> stack gate, no measurable <formula formulatype="inline"><tex Notation="TeX">$C$</tex></formula>–<formula formulatype="inline"><tex Notation="TeX">$V$</tex></formula> hysteresis and a smaller threshold voltage shift were observed, indicating that a high-quality interface can be achieved using a <formula formulatype="inline"><tex Notation="TeX">$\hbox{Al}_{2}\hbox{O}_{3}$</tex></formula> IPL on an AlGaN substrate. Good surface passivation effects of the <formula formulatype="inline"><tex Notation="TeX">$\hbox{Al}_{2}\hbox{O}_{3}$ </tex></formula> IPL have also been confirmed by pulsed gate measurements. Devices with 1- <formula formulatype="inline"><tex Notation="TeX">$\mu\hbox{m}$</tex></formula> gate lengths exhibit a cutoff frequency <formula formulatype="inline"><tex Notation="TeX">$(f_{T})$</tex></formula> of 12 GHz and a maximum frequency of oscillation <formula formulatype="inline"><tex Notation="TeX">$(f_{\rm MAX})$</tex></formula> of 34 GHz, as well as a maximum drain current of 800 mA/mm and a peak transconductance of 150 mS/mm, whereas the gate leakage current is at least six orders of magnitude lower than that of the reference high-electron mobility transistors at a positive gate bias. </para>