Experimental study on carrier transport limiting phenomena in 10 nm width nanowire CMOS transistors

Abstract

For the first time, we experimentally analyze the limiting scattering phenomena in gate-all-around nanowire CMOS transistors with aggressive dimensions (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> of 32 nm for NMOS and 42 nm for PMOS with 15 nm nanowire width) and with high-k/metal gate stacks. One-level and multiple-level stacked nanowire structures are measured and compared. The apparent carrier mobility is degraded in short channel devices. Moreover, we show that the interface quality has a major impact on nanowire transport properties. In rounded nanowires (thanks to H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> anneal), the extracted coulomb-limited mobility decreases whereas the surface roughness-limited mobility increases. Additionally, stacked nanowires suffer from additional coulomb scattering which is attributed to a degraded interface with high-k.