A Novel Device Architecture for SEU Mitigation: The Inverse-Mode Cascode SiGe HBT

Abstract

We investigate, for the first time, the potential for SEE mitigation of a newly-developed device architecture in a 3rd generation high-speed SiGe platform. This new device architecture is termed the ¿inverse-mode cascode SiGe HBT¿ and is comprised of two standard devices sharing a buried subcollector and operated in a cascode configuration. Verification of the TID immunity is demonstrated using 10 keV X-rays, while an investigation of the SEE susceptibility is performed using a 36 MeV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">16</sup> O ion. IBICC results show strong sensitivities to device bias with only marginal improvement when compared to a standard device; however, by providing a conductive path from the buried subcollector (C-Tap) to a voltage potential, almost all collected charge is induced on the C-Tap terminal instead of the collector terminal. These results are confirmed using full 3-D TCAD simulations which also provides insight into the physics of this new RHBD device architecture. The implications of biasing the C-Tap terminal in a circuit context are also addressed.