IEEE Electron Device Letters · 2003 · 120 citations · 14 references
EngineeringElectrical EngineeringElectronic MaterialsMicroelectronicsSemiconductor DevicesDevice CharacterizationDevice ModelingDevice ScalingHigh-frequency Semiconductor DevicesIntegrated Circuit DesignShort-channel EffectsChannel Length ScalingConductanceDevice OptimizationDevice Scaling EffectsHigh-frequency OperationHigh-frequency PerformanceParasitic CapacitanceParasitic Capacitance Reduction
Parameters limiting the improvement of high frequency characteristics for deep submicron MOSFETs with the downscaling process of the channel gate length are analyzed experimentally and analytically. It is demonstrated that for MOSFETs with optimized source, drain and gate access, the degradation of the maximum oscillation frequency is mainly related to the increase of the parasitic feedback gate-to-drain capacitance and output conductance with the physical channel length reduction. Optimization of these internal parameters is needed to further improve the high frequency performance of ultra deep submicron MOSFETs.
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