IEEE Transactions on Circuits and Systems for Video Technology · 2009 · 31 citations · 8 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureLow-power DesignSystem-on-chip DesignChannel CodingData CompressionHardware AccelerationImage CompressionLow-power Cache DesignRegister-transfer Level DesignCodec DecodingContext-based CompressionDigital Signal Processing AccelerationReal-time ProcessingReal-time Processing ArchitectureRegistersSequential DecodingVideo Compression
In this letter we propose a high-throughput VLSI architecture design for H.264 high-profile context-based adaptive binary arithmatic coding (HP CABAC) decoding for HDTV applications. To speed up the inherent sequential CABAC decoding, we eliminate the bottleneck by proposing a look-ahead decision parsing technique on the grouped context table with cache registers, which reduces 62% of cycle count on average as compared with the original CABAC decoding. In addition, the proposed design supports the macroblock adaptive frame field coding tools in H.264 main profile coding and 8 times 8 transform in H.264 high-profile coding. It achieves the real-time processing for H.264 CABAC decoding up to L4.1@30 frames/s with maximum 60 Mbits/s when operating at 105 MHz.
8