A high performance cabac decoding architecture

Abstract

In this paper, we propose a high performance hardware architecture of CABAC decoder CABAC is the context adaptive binary arithmetic coding used in H.264/AVC video standard, which achieves significant compression enhancement while bringing greater complexity and costs in implementation. The necessity of hardware implementation for real-time CABAC decoders is introduced, and then a fast and cost effective architecture is proposed. The new architecture can achieve decoding speed of averagely 500 cycles/macroblock, for typical 4M bit stream of DI resolution, 30 frame/s. An ASIC implementation of the new architecture is carried out in a 0.18 /spl mu/m silicon technology. The estimated area is 0.3 mm/sub 2/ and the critical path is limited within 6.7 ns.