Constant Addition utilizing Flagged Prefix Structures

Abstract

The role of addition and subtraction in digital systems is sometimes complicated due to the arrival of certain operands occurring at different times. For example, floating-point arithmetic typically requires the exponent logic to wait until an output is received from post-normalization. Previously, logic designers have resorted to the use of conditional sum and carry-select adders to make their design efficient. Recently, a new technique has been proposed that utilizes the concept of flagged prefix addition. Flagged prefix addition utilizes the parallel-prefix adder and slightly modifies it to yield a new adder that is capable of adding A+B or A+B+1. Moreover, alterations to the logic can easily be made to allow difference operations to occur as well. The paper presents an extension to flagged prefix addition to allow an arbitrary number to be added to the logic. Results are shown for several designs in AMI C5N 0.5 /spl mu/m technology.