Concepedia

Parallel Prefix Circuits

Parallel Prefix Circuits is a computational circuit architecture designed to efficiently compute prefix operations in parallel by hierarchically combining input values through associative binary operators, distinguished from other circuit models by its optimized structure for minimizing delay in parallel prefix computation.

125

Publications

6.2K

Citations

255

Authors

111

Institutions

Publications per year

2017–2026

27

Parents

Publications

125

Parallel Prefix Computation

Richard E. Ladner, Michael J. Fischer · Journal of the ACM · 1980 · 1.3K citations · Full text

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Fast area-efficient VLSI adders

Tack‐Don Han, David A. Carlson · 1987 · 315 citations

, , +15

Efficient VLSI implementation of modulo (2/sup n/±1) addition and multiplication

R. Zimmermann · 2003 · 305 citations

, , +15

A reduced-area scheme for carry-select adders

Akhilesh Tyagi · IEEE Transactions on Computers · 1993 · 241 citations

, , +16

The power of parallel prefix

Clyde P. Kruskal, Larry Rudolph, Marc Snir · IEEE Transactions on Computers · 1985 · 230 citations

, , +15

1–5 of 125

Authors

255

  1. HV
    H.T. Vergos

    University of Patras, Greece

    8 publications · 519 citations

    8

    h-index

  2. CE
    C. Efstathiou

    National and Kapodistrian University of Athens, Greece

    7 publications · 459 citations

    7

    h-index

  3. DN
    D. Nikolos

    University of Patras, Greece

    8 publications · 601 citations

    7

    h-index

  4. YL
    Yen‐Chun Lin

    Chiayi Chang Gung Memorial Hospital, Taiwan

    6 publications · 109 citations

    6

    h-index

  5. GD
    Giorgos Dimitrakopoulos

    Democritus University of Thrace, Greece

    5 publications · 255 citations

    5

    h-index

1–5 of 255

Institutions

111

  1. University of Patras

    Pátrai, Greece

    10 h-index

    22 publications

    1.4K citations

  2. Technological Educational Institute of Athens

    Athens, Greece

    7 h-index

    7 publications

    459 citations

  3. Computer Technology Institute and Press “DIOPHANTUS”

    Pátrai, Greece

    6 h-index

    13 publications

    648 citations

  4. National Taiwan University of Science and Technology

    Taipei, Taiwan

    5 h-index

    10 publications

    178 citations

  5. The University of Texas at Austin

    Austin, United States

    5 h-index

    9 publications

    254 citations

  6. Jaypee University of Information Technology

    Solan, India

    4 h-index

    12 publications

    291 citations

  7. IBM Research - Thomas J. Watson Research Center

    Yorktown Heights, United States

    3 h-index

    5 publications

    168 citations

  8. Yokohama National University

    Yokohama, Japan

    3 h-index

    6 publications

    197 citations

1–8 of 111

Venues

  1. IEEE Transactions on Computers

    14 publications · 1.3K citations

    14

    h-index

  2. 5

    h-index

  3. Journal of Parallel and Distributed Computing

    4 publications · 76 citations

    4

    h-index

  4. Microelectronics Journal

    4 publications · 90 citations

    4

    h-index

  5. Proceedings of the International Conference on Parallel Processing

    Conference · 3 publications · 56 citations

    3

    h-index

1–5