D. Nikolos - Concepedia

Author

D. Nikolos

University of Patras

Also Known As

D. G. Nikolos, D. NIKOLOS, D. Nikolos, D.G. Nikolos, Dimitrios Nikolos, Nikolos, D.

118

Publications

1.6K

Citations

H-Index

Concepts

All Affiliations

University of Patras Computer Technology Institute and Press “DIOPHANTUS”Technological Educational Institute of Athens National and Kapodistrian University of Athens National Centre of Scientific Research "Demokritos"

About

D. Nikolos is an author at University of Patras specializing in computer engineering, engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	19	34	1.2K
2	Computer Engineering	19	35	1.3K
3	Computer Science	14	22	717
4	Systems Engineering	8	8	145
5	Electrical Engineering	7	7	117

D. Nikolos

Publications

1.3K

Citations

H-Index

Page 1

	Year	Citations
High-speed parallel-prefix module 2/sup n/-1 adders L. Kalampoukas, D. Nikolos, C. Efstathiou, IEEE Transactions on Computers Hardware SecurityEngineeringVlsi DesignHardware AccelerationVlsi Architecture	2000	154
Diminished-one modulo 2/sup n/+1 adder design H.T. Vergos, C. Efstathiou, D. Nikolos IEEE Transactions on Computers EngineeringVlsi DesignComputational Number TheoryVlsi ArchitectureDiminished-one Modulo 2/Sup	2002	145
High-speed parallel-prefix VLSI Ling adders Giorgos Dimitrakopoulos, D. Nikolos IEEE Transactions on Computers Hardware SecurityEngineeringVlsi DesignVlsi ArchitectureCarry Equations	2005	134
Efficient Diminished-1 Modulo 2^n+1 Multipliers C. Efstathiou, H.T. Vergos, Giorgos Dimitrakopoulos, IEEE Transactions on Computers Hardware SecurityEngineeringComputational Number TheoryComputer EngineeringComputational Complexity	2005	83
Fast parallel-prefix modulo 2/sup n/+1 adders C. Efstathiou, H.T. Vergos, D. Nikolos IEEE Transactions on Computers EngineeringAdvanced ComputingComputer ArchitectureParallel ImplementationParallel-prefix Modulo 2/Sup	2004	80
Modified booth modulo 2/sup n/ - 1 multipliers C. Efstathiou, H.T. Vergos, D. Nikolos IEEE Transactions on Computers Less Partial ProductN/-1 MultipliersComputational Number TheoryCmos ImplementationsComputer Engineering	2004	72
Area-time efficient modulo 2/sup n/-1 adder design C. Efstathiou, D. Nikolos, John Kalamatianos IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing Hardware SecurityEngineeringVlsi DesignCircuit DesignVlsi Architecture	1994	63
Modulo 2/sup n/ ± adder design using select-prefix blocks C. Efstathiou, H.T. Vergos, D. Nikolos IEEE Transactions on Computers EngineeringVlsi DesignVlsi ArchitectureBlock DesignComputer Engineering	2003	62
Efficient design of totally self-checking checkers for all low-cost arithmetic codes D. Nikolos, A. Paschalis, G. Philokyprou IEEE Transactions on Computers Program CheckingEngineeringSelf-checking CheckersVerificationLow-cost Arithmetic Codes	1988	40
Efficient modular design of TSC checkers for m-out-of-2m codes A. Paschalis, D. Nikolos, C. Halatsis IEEE Transactions on Computers EngineeringHardware Verification LanguageError Control TechniqueVerificationComputer Architecture	1988	39

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