Publication | Closed Access
Fast area-efficient VLSI adders
311
Citations
0
References
1987
Year
Unknown Venue
EngineeringVlsi DesignComputer ArchitectureComputational ComplexityInterconnection Network ArchitecturePrefix ComputationHardware SecurityHigh-performance ArchitectureParallel ComputingComputer EngineeringComputer ScienceMicroelectronicsArea-efficient Vlsi AddersBinary AdditionHardware AccelerationGraph TheoryVlsi ArchitectureParallel ProgrammingVlsiDelay Time
The study focuses on binary addition, aiming to produce area‑time efficient VLSI adders. The paper investigates area‑time tradeoffs in VLSI prefix computation and seeks to design low‑latency, area‑efficient addition circuitry. A novel graph representation combining existing prefix‑computation graphs is introduced, achieving near‑lower‑bound VLSI area. Using this graph, VLSI adders with area O(n log n) and the lowest possible delay—i.e., the fastest area‑efficient adders—are realized.
In this paper, we study area-time tradeoffs in VLSI for prefix computation using graph representations of this problem. Since the problem is intimately related to binary addition, the results we obtain lead to the design of area-time efficient VLSI adders. This is a major goal of our work: to design very low latency addition circuitry that is also area efficient. To this end, we present a new graph representation for prefix computation that leads to the design of a fast, area-efficient binary adder. The new graph is a combination of previously known graph representations for prefix computation, and its area is close to known lower bounds on the VLSI area of parallel prefix graphs. Using it, we are able to design VLSI adders having area A = 0(n log n) whose delay time is the lowest possible value, i. e. the fastest possible area-efficient VLSI adder.