Fabrication and characterization of an InAlAs/InGaAs/InP ring oscillator using integrated enhancement- and depletion-mode high-electron mobility transistors

Abstract

The fabrication and characterization of an 11-stage ring oscillator utilizing integrated enhancement- and depletion-mode (E/D-mode) high-electron mobility transistors (HEMT's) in the lattice-matched InAlAs/InGaAs/InGaAs material system is demonstrated. The 0.5-μm gate length depletion-mode HEMT's (D-HEMT's) used in the circuit exhibit a threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of -365 mV with a standard deviation of 19 mV, while the enhancement-mode HEMT's (E-HEMT's) with identical gate length display a V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of 195 mV with a standard deviation of only 9 mV. The unity current gain cutoff frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) for both devices is 70 GHz. The extremely high uniformity of the threshold voltages of these devices allowed for the implementation of a ring oscillator utilizing direct coupled FET logic (DCFL). At a supply voltage of 0.4 V, a room temperature propagation delay time (/spl tau//sub pd/) of 22.4 ps/stage, and a corresponding power dissipation of 120 μW/stage is measured, yielding a power delay product (PDP) of 2.65 fJ/stage. To the best of the authors knowledge, this is the first demonstration of a circuit employing E/D-HEMT technology in the lattice-matched InP-based material system.