IEEE Transactions on Circuits & Systems II Express Briefs · 2011 · 34 citations · 11 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysReconfigurable ComputingConfigurable Logic BlocksDynamic ReconfigurationField-programmable Gate Array ArchitectureFpga ArchitectureReconfigurable System ArchitectureVery-large-scale Integration LayoutMultiplier DesignMultipliersReal-time ProcessingReconfigurable ArchitecturesReconfigurable Hardware ArchitectureReconfigurationStatic ReconfigurationVlsi Implementation
This brief presents a reconfigurable VLSI architecture which is designed for multi-transform codec in several video coding standards of MPEG-2/4, VC-1, H.264/AVC and AVS. The reconfigurable multiple constant multiplication algorithm with two fusing strategies is provided to generate constant multipliers in the matrix calculation blocks. Additionally, adder-sharing strategy is adopted in the unified preprocessing/postprocessing block to save circuit areas. The proposed architecture can support different standards through static reconfiguration and forward/inverse transform functions through dynamic reconfiguration. It is suitable for the real-time processing of 1080P HD video codec with six video standards transforms.
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Parallel 4×4 2D transform and inverse transform architecture for MPEG-4 AVC/H.264
Tu-Chih Wang, Yu‐Wen Huang, Hung-Chi Fang et al. · 2003 · 121 citations