Reconfigurable Architectures is a spatial accelerator architecture that enables dynamic modification of its hardware structure and connectivity during runtime to adapt to varying computational patterns and optimize execution efficiency.
1.7K
Publications
69.5K
Citations
4.2K
Authors
919
Institutions
Publications per year
2017–2026
340
Publications
1.7K
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
Chen Zhang, Peng Li, Guangyu Sun et al. · 2015 · 2.1K citations
Garp: a MIPS processor with a reconfigurable coprocessor
John R. Hauser, John Wawrzynek · 2002 · 794 citations
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Authors
4.2K
- SH
22
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- WL
18
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- LL
16
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- SY
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- JB
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1–5 of 4.2K
Institutions
919
Imperial College London
London, United Kingdom
23 h-index
115 publications
6.6K citations
University of Washington
Seattle, United States
22 h-index
58 publications
5.5K citations
Nanyang Technological University
Singapore, Singapore
20 h-index
72 publications
2.9K citations
University of California, Los Angeles
Los Angeles, United States
19 h-index
60 publications
10.4K citations
University of California, Irvine
Irvine, United States
19 h-index
72 publications
6.6K citations
Tsinghua University
Beijing, China
19 h-index
134 publications
6.2K citations
Stanford University
Stanford, United States
19 h-index
158 publications
9K citations
University of Kaiserslautern
Kaiserslautern, Germany
17 h-index
57 publications
2.2K citations
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Venues
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
44 publications · 2.3K citations
26
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- IEEE Transactions on Computers
29 publications · 2.4K citations
19
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- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
23 publications · 1.1K citations
17
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- IEEE Transactions on Parallel and Distributed Systems
TPDS · 15 publications · 433 citations
14
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- ACM Transactions on Reconfigurable Technology and Systems
19 publications · 559 citations
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