European Design Automation Conference · 1994 · 17 citations · 19 references
EngineeringComputer EngineeringComputer ScienceField-programmable Gate ArraysReconfigurable ComputingSystem-on-chip DesignConfigurable Logic BlocksData PartitioningField-programmable Gate Array ArchitectureFpga ArchitectureHardware Modeling For Digital SystemsLogic SynthesisChip PartitioningCost Model OptimizationDigital Logic CircuitsHardware PartitioningHeterogeneous Fpga ArchitecturesPartitioning AlgorithmsPartitioning In System-on-chip DesignTerminal Constraints
This paper introduces the concept of functional replication and a unifled cost model for min-cut partitioning with replication. We apply this concept to the problem of partitioning large logic circuits into a collection of subcir- cuits each of which is implemented with a device from a speciflc (FPGA) library. We measure the quality of each k-way partition not only in in terms of the minimum size of the cutset but also the total device cost, the average utilization of logic as well as the terminal capacity. Bench- mark results show signiflcant improvements in the size of the cutset when partitioning without terminal constraints as well as when partitioning with size and terminal con- straints.
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Laura A. Sanchis · IEEE Transactions on Computers · 1989 · 386 citations
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