Power-aware variable partitioning for DSPs with hybrid PRAM and DRAM main memory

Abstract

In this paper, we utilize a hybrid main memory composed of DRAM and Phase Change Random Access Memory (PRAM) for DSP systems, which leverages the low power consumption of PRAM while minimizing the performance and endurance degradation caused by write operations on PRAM. We re-consider the variable partitioning problem on this hybrid main memory. Different objectives, for example power consumption and the number of writes on PRAM, are considered in this paper. By using the proposed models and algorithms, experiments show that we can reduce 53% power consumption and 79% the number of writes on PRAM on average, compared with pure DRAM and pure PRAM memory, respectively.