Architecting phase change memory as a scalable dram alternative

TLDR

Memory scaling is threatened for DRAM due to unreliable charge storage and sensing, whereas phase‑change memory relies on scalable current and thermal mechanisms. The study aims to exploit PCM’s scalability as a DRAM alternative. The authors propose area‑neutral architectural enhancements derived from PCM technology parameters to reduce latency, energy writes, and improve endurance. Baseline PCM is 1.6× slower and 2.2× more energy‑intensive than DRAM, but buffer reorganizations reduce the delay to 1.2× and energy to parity, while partial writes extend endurance to 5.6 years, with further gains expected from process scaling.

Abstract

Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as DRAM. In contrast, phase change memory (PCM) storage relies on scalable current and thermal mechanisms. To exploit PCM's scalability as a DRAM alternative, PCM must be architected to address relatively long latencies, high energy writes, and finite endurance. We propose, crafted from a fundamental understanding of PCM technology parameters, area-neutral architectural enhancements that address these limitations and make PCM competitive with DRAM. A baseline PCM system is 1.6x slower and requires 2.2x more energy than a DRAM system. Buffer reorganizations reduce this delay and energy gap to 1.2x and 1.0x, using narrow rows to mitigate write energy and multiple rows to improve locality and write coalescing. Partial writes enhance memory endurance, providing 5.6 years of lifetime. Process scaling will further reduce PCM energy costs and improve endurance.