TFSOI CMOS technology for sub-1 V microcontroller circuits

Abstract

For the first time, a sub-1 V microcontroller CPU core is demonstrated using Thin-Film-Silicon-On-Insulator (TFSOI) CMOS technology. Yield sensitivity of the microcontroller circuit blocks (including the CPU, SRAM and ROM) to variations of the 0.5 /spl mu/m process technology is investigated. The low-voltage circuit yield of the CPU is found to be more sensitive to isolation stress-induced device defect leakage than the SRAM and ROM circuits. The stress-induced leakage also causes abnormal frequency vs. V/sub DD/ behavior with the CPU. CPU yield comparable to bulk CMOS, combined with a /spl sim/2/spl times/ maximum clock frequency enhancement, is achieved with the optimized low-leakage TFSOI process.