A neuron MOS transistor-based multiplier cell

W. Weber, S.J. Prange, R. Thewes, E. Wohlrab

2002 · 13 citations · 3 references

Concepts

Abstract

Based on the neuron MOS transistor principle a multiplier circuit is designed for the first time. High-speed measurements are presented that qualify the principle of threshold logic for a new design principle. This represents a major breakthrough of packing density improvement of CMOS-based logic applications.

References

3