2007 · 35 citations · 7 references
EngineeringComputer EngineeringComputer ArchitectureDesign OptimizationLow-power DesignDynamic Power ReductionFpga ArchitecturePower ManagementPower OptimizationPower-aware DesignRoutingDynamic Power DissipationDynamic Power ModelingPower Consumption OptimizationPower ModelPower-aware Fpga ArchitecturePower-aware PlacementPower-efficient ArchitecturePower-efficient Design
We consider dynamic power dissipation in FPGAs and present CAD techniques for dynamic power reduction. The proposed techniques, comprising power-aware placement, routing, and a novel post-routing transformation, are applied to optimize the power consumed by industrial designs implemented in the Xilinx® Virtex™-5 FPGA. Board-level power measurements on a suite of industrial designs show that the techniques reduce power by 10%, on average.
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Dynamic power consumption in Virtex™-II FPGA family
Li Shang, Alireza Kaviani, Kusuma Bathala · 2002 · 393 citations
Leakage power analysis of a 90nm FPGA
Tim Tuan, B. Lai · 2004 · 165 citations
Engineering, Computer Engineering, Electrical Engineering +17