Analysis of Soft Error Mitigation Techniques for Register Files in IBM Cu-08 90nm Technology

Abstract

Soft errors are a major reliability concern for today's nanometer technologies. The errors in register files in Application Specific Integrated Circuits (ASIC) can quickly spread to various parts of the system and result in data corruption which may go unnoticed. Single Error Correction (SEC) Hamming code and Triple Modular Redundancy (TMR) provide a high-level mitigation solution for soft errors. The experimental results presented in this work for a 64-bit wide, 32-word entry register file, synthesized for IBM Cu-08 (90nm) standard cell ASIC technology, show that TMR is a better solution for latency sensitive ASIC applications. This technique increases the read access time by only 17% but incurs 204% area penalty. Whereas SEC applied on the 64-bit word size incurs 129% increase in read access time with area penalty only about 22%. This large read access penalty for applying SEC on wide words makes it necessary to partition the word into smaller block sizes before applying SEC. The design space explored in this work, for various combinations of word and block sizes, shows that Hamming code provides a reasonable spectrum of choice to trade-off between area and latency of fault-tolerant register files.