Scaling to 50-nm C-axis aligned crystalline In-Ga-Zn oxide FET with surrounded channel structure and its application for less-than-5-nsec writing speed memory

Abstract

We report novel FETs with a structure in which not only the top surface but also the side surfaces of island-shaped c-axis aligned crystalline indium-gallium-zinc oxide (CAAC-IGZO) serving as a channel are surrounded by a gate electrode, that is, surrounded channel CAAC-IGZO FETs. The FETs maintained their favorable subthreshold characteristics even if the channel length was scaled down to approximately 50 nm, i.e., normally-off, DIBL of 67 mV/V, SS of 92 mV/dec, and an off-state current lower than the measurement limit (0.1 pA) for a gate insulating film EOT of 11 nm. Moreover, we applied an FET with such a structure to a memory and discussed the writing time and the retention time, which were expected to be less than 5 ns and greater than 1,000 sec, respectively, for storage capacitance of 1 fF from circuit simulation.