A high density floating-gate EEPROM cell

Abstract

An electrically erasable PROM cell is described which is implemented in a N-channel double polysilicon gate process. The cell is composed of a double poly floating-gate memory device and a select transistor. Electrical programming and erasure of the floating-gate transistor is achieved by field emission of electrons through a thin oxide. The memory transistor exhibits an endurance of greater than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> program-erase cycles with extrapolated data retention in excess of ten years. The cell has been used to develop a 32K EEPROM memory chip which operates from a single +5 volt supply during read. Typical access time is 100 ns. An extra +21 volt DC supply is used to program or erase the device in less than 10 ms.