Design Automation Conference · 1981 · 13 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsVlsi DesignCmos Circuit DesignCombinational Logic DescriptionDelay ModelingDigital Integrated Circuit DesignDigital Logic DesignSystem SimulationCircuit SimulationCmos Logic CircuitsCombinational Logic DesignDelay SimulationGate Delay ModelingGate-level ModelingInertial DelayTransmission Gate Logic
A logic simulator capable of efficiently modelling complex MOS/LSI circuits is presented. The circuit is simulated at the combinational logic and transmission gate level using a set of six node-states. Gate models have inertial delay and assignable nominal rise and fall delays. Both unidirectional and bidirectional transmission gates are accurately simulated, and functional models are provided for ROM, RAM, etc.
6
High-speed concurrent fault simulation with vectors and scalars
E. Ulrich, D. Lacy, Nolan Edward Phillips et al. · 1980 · 44 citations