Transmission Gate Logic

Transmission Gate Logic is a CMOS logic design methodology that employs complementary transistor pairs as bidirectional switches to pass both logic high and low signals without degradation, distinguishing it from conventional static logic families that rely on pull-up and pull-down networks.

92

Publications

3.1K

Citations

287

Authors

118

Institutions

Publications per year

2017–2026

21

Variants

Transmission Gate Cmos Logic

Authors

287

  1. SM
    Sanu Mathew

    Intel (United States), United States

    2 publications · 84 citations

    2

    h-index

  2. NK
    Nehru Kandasamy

    GITAM University, India

    2 publications · 48 citations

    2

    h-index

  3. NR
    Nihar R. Mahapatra

    Michigan State University, United States

    2 publications · 116 citations

    2

    h-index

  4. PG
    Pierre‐Emmanuel Gaillardon

    École Polytechnique Fédérale de Lausanne, Switzerland

    2 publications · 64 citations

    2

    h-index

  5. NS
    Nabiollah Shiri

    Islamic Azad University of Shiraz, Iran

    2 publications · 58 citations

    2

    h-index

1–5 of 287

Venues

  1. IEEE Journal of Solid-State Circuits

    10 publications · 325 citations

    10

    h-index

  2. International Journal of Electronics

    3 publications · 124 citations

    3

    h-index

  3. 3

    h-index

  4. IEEE Transactions on Electron Devices

    2 publications · 91 citations

    2

    h-index

  5. 2

    h-index

1–5