Transmission Gate Logic
Transmission Gate Logic is a CMOS logic design methodology that employs complementary transistor pairs as bidirectional switches to pass both logic high and low signals without degradation, distinguishing it from conventional static logic families that rely on pull-up and pull-down networks.
92
Publications
3.1K
Citations
287
Authors
118
Institutions
Publications per year
2017–2026
21
Variants
Transmission Gate Cmos Logic
Parents
92
Reversible electronic logic using switches
Ralph C. Merkle · Nanotechnology · 1993 · 178 citations
Engineering, Computer Engineering, Electrical Engineering +17
A new cell for low power adders
E. Abu-Shama, Magdy Bayoumi · 1996 · 94 citations
Engineering, Computer Engineering, Electrical Engineering +17
1–5 of 92
287
2
h-index
2
h-index
2
h-index
École Polytechnique Fédérale de Lausanne, Switzerland
2 publications · 64 citations
2
h-index
2
h-index
1–5 of 287
118
École Polytechnique Fédérale de Lausanne
Lausanne, Switzerland
3 h-index
9 publications
287 citations
University at Buffalo, State University of New York
Buffalo, United States
3 h-index
7 publications
335 citations
Nanyang Technological University
Singapore, Singapore
3 h-index
6 publications
166 citations
International Institute of Information Technology, Hyderabad
Hyderabad, India
2 h-index
8 publications
168 citations
New York University
New York, United States
2 h-index
5 publications
249 citations
Ningbo University
Ningbo, China
2 h-index
4 publications
48 citations

North South University
Dhaka, Bangladesh
2 h-index
8 publications
296 citations
Intel (United States)
Santa Clara, United States
2 h-index
14 publications
588 citations
1–8 of 118
10 publications · 325 citations
10
h-index
3 publications · 124 citations
3
h-index
3 publications · 420 citations
3
h-index
2 publications · 91 citations
2
h-index
2 publications · 57 citations
2
h-index
1–5