2007 · 20 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsVlsi DesignCmos Circuit DesignLow-power Digital Circuit DesignPower ManagementPower OptimizationTiming AnalysisVoltage ScalingCmos Logic CircuitsCmos Logic DesignCurrent-mode LogicHigh-speed Logic DesignLow-power Cmos DesignLow-power Logic DesignPower-delay ProductPower-delay Tradeoff
In this paper, the authors study the operation of MOS current-mode logic (MCML) gates at lower-than-nominal supply voltages. The authors show that power can be traded for speed by reducing the supply voltage below the nominal value, while the power-delay product stays nearly constant. The authors propose a negative bias strategy that enables the gates to operate at maximum speed with a reduced supply voltage, thus achieving a power saving of up to 35% at no cost for speed. Comparison with CMOS logic style are presented for three different technology nodes (0.25 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m, 0.18 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m and 0.13 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m CMOS).
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