EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignDevice ModelingDevice ScalingIntegrated Circuit DesignNoise In Semiconductor DevicesPower ManagementCmos Digital Circuit DesignCmos Logic CircuitsCmos ScalingCurrent-mode Circuit DesignCurrent-mode LogicLow-power Cmos DesignProcess Variation AnalysisScaling Effects In Cmos
The effect of on-chip process variations on MOS current mode logic (MCML) performance is explored. A closed form expression for the noise-margin is derived. On-chip process variations are shown to set the lower limit for the power dissipation of an MCML family.
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Analysis and Design of Analog Integrated Circuits
W.R. Betts · Electronics and Power · 1978 · 3.8K citations