Challenges of high-k gate dielectrics for future MOS devices

Abstract

As the feature sizes of complementary metal-oxide-semiconductor (CMOS) devices are scaled downward, the gate dielectric thickness must also decrease to maintain a value of capacitance to reduce short-channel effects and to keep device drive current at an acceptable level. The Semiconductor Industry Association's (SIA) International Technology Roadmap for Semiconductors (ITRS) indicates that by the years 2003-2005, the equivalent thickness of the gate dielectric will need to be approximately 1.5 nm. Reducing the thickness of SiO/sub 2/ to these dimensions results in an exponential increase of direct tunneling current. It has been suggested that SiO/sub 2/ as thin as 1.6 nm may be tolerable in terms of intrinsic reliability (Weir et al, 1999) and leakage (Henson et al, 2000) for high performance applications. Although the exact thickness limit for SiO/sub 2/ is debatable, at some technology node the use of SiO/sub 2/ as the gate dielectric will no longer be possible. A suitable replacement gate dielectric with high permittivity (k) must exhibit low leakage current, have the ability to be integrated into a CMOS process flow, and exhibit at least the same equivalent capacitance, performance, and reliability of SiO/sub 2/. Many candidate possible high-k gate dielectrics have been suggested to replace SiO/sub 2/. The purpose of this overview is to discuss the general requirements and challenges associated with these materials as possible gate dielectrics. Issues to be discussed include processing, dielectric constant, capacitance, bandgap, tunnel current, and reliability.