2007 · 110 citations · 7 references
EngineeringComputer EngineeringElectrical EngineeringEmbedded SystemsLow-power DesignMicroelectronicsCmos Circuit DesignDigital Integrated Circuit DesignEnergy-efficient Embedded SystemsIntegrated Circuit DesignLow-power Digital Circuit DesignTiming AnalysisAdder DesignLow-power AddersLow-power Cmos DesignPass-transistor LogicPower ConsumptionPower-delay ProductStatic Cmos CircuitsStatic Cmos Logic
In this paper, a low-power high-speed CMOS full adder core is proposed for embedded system. Based on a new three-input exclusive OR (3-XOR) design, the new hybrid full adder is composed of pass-transistor logic and static CMOS logic. The main design objectives for the full adder core are providing not only low power and high speed but also with driving capability. Using TSMC CMOS 0.35-mum technology, the characteristics of the experimental circuit compared with prior literature show that the new adder improves 1.8% to 35.6% in power consumption, 11.7% to 41.2% in time delay of Co, and 13.7% to 91.4% in power-delay product of Co. The circuit is proven to have the minimum power consumption and the fastest response of carry out signal among the adders selected for comparison. Due to the low-power and high-speed properties, both the new exclusive OR circuit and the new full adder can be efficiently integrated in a system-on-a-chip (SoC) or an embedded system.
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A new design of the CMOS full adder
Nan Zhuang, Haomin Wu · IEEE Journal of Solid-State Circuits · 1992 · 322 citations
Engineering, Computer Engineering, Electrical Engineering +13
Principles of CMOS VLSI design
1993 · 124 citations
Engineering, Computer Engineering, Electrical Engineering +12
On the design of low-energy hybrid CMOS 1-bit full adder cells
S. Goel, S. Gollamudi, Ashok Kumar et al. · 2004 · 41 citations
Engineering, Computer Engineering, Electrical Engineering +17