Integration of high aspect ratio tapered silicon via for through-silicon interconnection

Abstract

This paper provides a detailed overview of silicon carrier based packaging for 3D system in packaging application. In this work the various critical process modules that play a vital role in the integration and fabrication of silicon carrier with high aspect ratio tapered through-silicon interconnections have been explained and discussed with experimental data. A method of fabricating tapered deep silicon via in a 3-step approach has been developed and characterized which controls via depth, sidewall profile and surface roughness effectively. A low-temperature dielectric deposition process is also developed that has minimum residual stress and good dielectric coverage on the via sidewall. The above processes were then integrated with back-end processes like seed metallization, copper electroplating, chemical mechanical polishing and wafer thinning to realize a fully integrated silicon carrier fabrication technology. The silicon carriers were finally assembled and tested for through silicon interconnection.