A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects

Abstract

A viable approach for a monolithic wafer-scale three-dimensional (3D) IC technology platform is presented, focusing on wafer bonding, wafer thinning and inter-wafer damascene-patterned interconnects. Principal results include successful wafer alignment, wafer bonding with both BCB and Flare, post bonding wafer thinning using grinding and polishing to 35-50 /spl mu/m, and via etch through the required material stack.