A 1.2-V 12-b 120-MS/s SHA-Free Dual-Channel Nyquist ADC Based on Midcode Calibration

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper describes a 12-b 120-MS/s dual-channel pipeline analog-to-digital converter (ADC) for high-speed video signal processing. A simple digital midcode calibration technique is proposed to eliminate an offset mismatch between two channels. The proposed sample-and-hold-amplifier-free architecture with correlated input sampling networks enables wideband signal sampling while effectively reducing a gain mismatch between channels. The prototype ADC implemented in a 0.13-<formula formulatype="inline"><tex Notation="TeX">$\mu{\hbox {m}}$</tex> </formula> CMOS technology achieves a peak signal-to-noise-and-distortion ratio of 61.1 dB and a peak spurious-free dynamic range of 74.7 dB for input frequencies up to 60 MHz at 120 MS/s. The measured differential and integral nonlinearities are within <formula formulatype="inline"><tex Notation="TeX">$\pm 0.30$</tex></formula> LSB and <formula formulatype="inline"><tex Notation="TeX">$\pm 0.95$</tex></formula> LSB, respectively. The ADC occupies an active die area of <formula formulatype="inline"><tex Notation="TeX">$0.56~{\hbox {mm}}^{2}$</tex> </formula> and consumes 51.6 mW at a 1.2 V power supply. </para>