Time interleaved converter arrays

TLDR

Flash ADCs use many comparators in parallel to achieve high bandwidth, but this approach is area‑inefficient and leads to large die sizes even for modest resolution. The authors aim to match flash‑speed performance while dramatically reducing area by time‑interleaving several small, area‑efficient converters. They implement a four‑way array of 7‑bit weighted‑capacitor ADCs in a 10 µm CMOS process, analyze noise and distortion from nonideal array characteristics, and describe anticipated performance in a modern 4–5 µm process. The prototype achieves full 7‑bit linearity up to 2.5 MHz, with acceptable linearity up to about 4 MHz.

Abstract

High-speed monolithic converters normally use a variation of the flash technique, which 2/SUP n/ comparators in parallel to obtain a fast n-bit conversion. Although this method allows for high converter bandwidth, it is not very area efficient, and results in large die sizes for even modest resolution converters. In the technique presented here, a number of small but area efficient converters are operated in a time-interleaved fashion to achieve the bandwidth of a flash circuit, but in a substantially smaller area. This technique is analyzed with respect to noise and distortion resulting from nonideal array characteristics, and is demonstrated by way of a four-way array test-chip. This chip consists of four time-interleaved 7-bit weighted-capacitor A/D converters fabricated in a 10 /spl mu/m metal-gate CMOS process. Full 7-bit linearity is maintained up to a 2.5 MHz conversion rate, with operation at reduced linearity continuing to approximately 4 MHz. The design of this chip, and anticipated characteristics if fabricated in a modern 4-5 /spl mu/m process are described.