IEEE Transactions on Computers · 1997 · 72 citations · 19 references
ComputingComputer EngineeringComputer ScienceAlgorithmsFault-tolerant ComputingFault-tolerant SystemsDesign For TestabilityError DetectionFault DetectionLookup TablesSoftware TestingCombinational Circuit VerificationDesign For Testability CheckingError Detection Circuits
This paper presents a design method of easily testable AND-EXOR networks. It is an improvement of Reddy (1972) and Saluja-Reddy's (1975) methods, and has the following features. The network uses generalized Reed-Muller expressions (GRMs) instead of Positive Polarity Reed-Muller expressions (PPRMs). The average number of products for GRMs is less than half of that for PPRMs, and is less than that of sum-of-products expressions (SOPs). The network consists of a literal part, an AND part, an EXOR part, and a check part. The EXOR part can be a tree instead of a cascade. Thus, the network is faster. The test detects multiple stuck at faults under the assumption that the faults occur at most one part, either the literal part, the AND part, the EXOR part, or the check part.
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Logic Testing and Design for testability
Computer-Aided Design · 1986 · 324 citations
Discrete and switching functions.
Mathematics and Computers in Simulation · 1979 · 295 citations
Easily Testable Realizations ror Logic Functions
S.M. Reddy · IEEE Transactions on Computers · 1972 · 278 citations
On the complexity of mod-2l sum PLA's
T. Sasao, Philipp W. Besslich · IEEE Transactions on Computers · 1990 · 180 citations