Combinational Circuit Verification

Combinational Circuit Verification is the formal process of systematically checking whether a combinational circuit correctly implements its specified logical functionality under all possible input conditions, distinguishing it from sequential verification by excluding time-dependent behavior.

127

Publications

4.5K

Citations

248

Authors

109

Institutions

Publications per year

2017–2026

5

Authors

248

  1. AS
    Alberto Sangiovanni‐Vincentelli

    University of California, Berkeley, United States

    5 publications · 117 citations

    5

    h-index

  2. SM
    Sharad Malik

    Princeton University, United States

    5 publications · 170 citations

    5

    h-index

  3. SR
    S.M. Reddy

    University of Iowa, United States

    5 publications · 316 citations

    5

    h-index

  4. VD
    Vishwani D. Agrawal

    AT&T (United States), United States

    5 publications · 221 citations

    5

    h-index

  5. JJ
    J. Jain

    Fujitsu (United States), United States

    4 publications · 114 citations

    4

    h-index

1–5 of 248

Venues

  1. IEEE Transactions on Computers

    12 publications · 846 citations

    12

    h-index

  2. 12

    h-index

  3. Automation and Remote Control

    3 publications · 75 citations

    3

    h-index

  4. International Conference on Computer Aided Design

    Conference · 3 publications · 65 citations

    3

    h-index

  5. Integration

    2 publications · 91 citations

    2

    h-index

1–5