Combinational Circuit Verification
Combinational Circuit Verification is the formal process of systematically checking whether a combinational circuit correctly implements its specified logical functionality under all possible input conditions, distinguishing it from sequential verification by excluding time-dependent behavior.
127
Publications
4.5K
Citations
248
Authors
109
Institutions
Publications per year
2017–2026
5
127
IRSIM: an incremental MOS switch-level simulator
Arturo Salz, Mark Horowitz · 1989 · 152 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +16
1–5 of 127
248
University of California, Berkeley, United States
5 publications · 117 citations
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1–5 of 248
109
University of Michigan
Ann Arbor, United States
6 h-index
11 publications
240 citations
Princeton University
Princeton, United States
6 h-index
8 publications
272 citations
University of Potsdam
Potsdam, Germany
6 h-index
9 publications
342 citations
Synopsys (United States)
Mountain View, United States
6 h-index
14 publications
210 citations
Fujitsu (United States)
Sunnyvale, United States
6 h-index
13 publications
393 citations
University of Iowa
Iowa City, United States
6 h-index
8 publications
540 citations
University of California, Berkeley
Berkeley, United States
5 h-index
9 publications
386 citations
Cadence Design Systems (United States)
San Jose, United States
4 h-index
5 publications
215 citations
1–8 of 109
12 publications · 846 citations
12
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13 publications · 640 citations
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3 publications · 75 citations
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Conference · 3 publications · 65 citations
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2 publications · 91 citations
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