High-$\kappa$/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Schottky source/drain (S/D) MOSFETs hold the promise for low series resistance and extremely abrupt junctions, providing a path for device scaling in conjunction with a low Schottky barrier height (SBH). A S/D junction SBH approaching zero is also needed to achieve a competitive current drive. In this letter, we demonstrate a CMOS process flow that accomplishes a reduction of the S/D SBH for nFET and pFET simultaneously using implants into a common NiPt silicide, followed by a low-temperature anneal (500 <formula formulatype="inline"><tex Notation="TeX">$^{\circ} \hbox{C}$</tex></formula>–600 <formula formulatype="inline"><tex Notation="TeX">$^{\circ}\hbox{C}$</tex></formula>). These devices have high-<formula formulatype="inline"><tex Notation="TeX">$\kappa$</tex></formula>/metal gate and fully depleted extremely thin SOI with sub-30-nm gate length. </para>