A delay-locked loop and 90-degree phase shifter for 100 Mbps double data rate memories

Abstract

Recent high-speed DRAMs adopt the architecture known as DDR (Double Data Rate) in which data are sent out at both rising and falling edges of the system clock. In order to capture the incoming data, the 90-degree phase shifter is used to shift the phase of the system clock to the center of the data period. Conventional 90-degree shifters have been organized from the PLL. In this paper, the 90-degree phase shift is achieved without a PLL. This shifter is also able to reduce the influence of the clock duty error.