Y. Morooka

A 45-ns 64-Mb DRAM with a merged match-line test architecture

S. Mori, Hiroshi Miyamoto, Y. Morooka et al. · IEEE Journal of Solid-State Circuits · 1991 · 24 citations

Engineering, Vlsi Design, Mem Testing +16

An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs

Y. Tsukikawa, Takeshi Kajimoto, Y. Okasaka et al. · IEEE Journal of Solid-State Circuits · 1994 · 21 citations

Low-power Electronics, Electrical Engineering, Engineering +11

A delay-locked loop and 90-degree phase shifter for 100 Mbps double data rate memories

Tsutomu Yoshimura, Y. Nakase, Naoya Watanabe et al. · 2002 · 17 citations

Recent High-speed Drams, Engineering, Double Data Rate +12

AN ADDRESS MASKABLE PARALLEL TESTING FOR ULTRA HIGH DENSITY DRAMS

Y. Morooka, S. Mori, Hiroshi Miyamoto et al. · 2005 · 12 citations

Hardware Security, Electrical Engineering, Memory Architecture +11

An adjustable output driver with a self-recovering Vpp generator for a 4M×16 DRAM

K. Furutani, Hiroshi Miyamoto, Y. Morooka et al. · IEEE Journal of Solid-State Circuits · 1994 · 12 citations

Electrical Engineering, Engineering, Vlsi Design +8