2002 · 32 citations · 8 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysReconfigurable ComputingApplication-specific Integrated CircuitsConfigurable Logic BlocksField-programmable Gate Array ArchitectureFpga ArchitectureLookup TablesPower OptimizationArea EfficiencyArea-efficient Fpga ArchitectureArea-efficient Logic Block DesignField-programmable Gate Arrays (Fpgas)Heterogeneous Field-programmable Gate Array ArchitectureHeterogeneous Fpga ArchitecturesLogic Block DesignPins
The authors consider field programmable gate arrays (FPGAs) that use two different sizes of lookup table (LUT) logic blocks and investigate the area-efficiency of different mixtures of different sizes of LUTs. Experimental results on a set of benchmark circuits indicate that several heterogeneous architectures achieve significant reduction in the number of programming bits and logic block pins compared to the industry standard 4-input LUTs. A 6-LUT/4-LUT combination will likely exhibit better performance with nearly equivalent area than a homogeneous 4-LUT FPGA.
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Third-generation architecture boosts speed and density of field-programmable gate arrays
Harry Hsieh, W.S. Carter, J.Y. Ja et al. · 2002 · 116 citations
The effect of logic block architecture on FPGA performance
Sarjana Singh, Jonathan Rose, Paul Chow et al. · IEEE Journal of Solid-State Circuits · 1992 · 98 citations