Third-generation architecture boosts speed and density of field-programmable gate arrays

Abstract

Using a combination of architectural and process improvements, a third-generation family of field-programmable gate arrays (FPGAs) features up to twice the density and speed of currently-available FPGA devices. The architecture was devised to allow complete and efficient automated design implementation of FPGA-based designs, as well as maximum density and performance. This architecture is described. User-configurable on-chip static memory resources further contribute to the high integration levels available to users of the third-generation devices.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>