Selective CVD tungsten via plugs for multilevel metallization

Abstract

Use of selective-metal CVD tungsten is shown to be a viable method of filling small via holes in multilevel metal integrated circuits. The method specifically described utilizes Mo/TiW as the first-level interconnection/contacting metallization (M1), a planarized interlevel dielectric, straight via holes filled with tungsten, and AL second-level metal (M2). This methodology solves the problems of variable via depth encountered in integrated circuits especially when interlevel dielectrics are planarized and whenever design rules are utilized which allow for stacked and unstacked via connections to underlying features at widely varying topological height. The method also provides a means of greatly reducing metal interconnection pitch.