Test responses compaction in accumulators with rotate carry adders

Abstract

An accumulator-based compaction (ABC) scheme for parallel compaction of test responses is presented. In this scheme an accumulator with an n-bit binary adder is slightly modified such that the quality of compaction defined by the asymptotic coverage drop is similar to that offered by shift registers with irreducible polynomials of cellular automata. A Markov-chain model is used to analyze both the asymptotic coverage drop introduced by this scheme, and its transient behavior. It is shown that the asymptotic coverage drop depends both on the size of the accumulator and the probability of a fault injection. The upper bound of the coverage drop during the transition phrase is also provided. The proposed scheme is compatible with the width of the data path, and the test can be applied at the normal mode speed. The minimal hardware overhead involves only one-bit register to implement the feedback between the carry-out and carry-in lines.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>