Supply and threshold-Voltage trends for scaled logic and SRAM MOSFETs

Abstract

The authors show new guidelines for V/sub dd/ and threshold voltage (V/sub th/) scaling for both the logic blocks and the high-density SRAM cells from low power-dissipation viewpoint. For the logic operation, they have estimated the power and the speed for inverter gates with a fanout=3. They find that the optimum V/sub dd/ is very sensitive to switching activity in addition to the operation frequency. They propose to integrate two sets of transistors having different V/sub dd/s on a chip. In portions of the chip with high frequency or high switching activity, the use of H transistors in which V/sub dd/ and V/sub th/ are moderately scaled is helpful. On the other hand, in low switching activity blocks or relatively low frequency portions, the use of L transistors in which V/sub dd/ should be kept around 1-1.2 V is advantageous. A combination of H and L is beneficial to suppress power consumption in the future. They have investigated the yield of SRAM arrays to study the optimum V/sub dd/ for SRAM operation. In high-density SRAM, low V/sub th/ causes yield loss and an area penalty because of low static noise margin and high bit leakage especially at high temperature operation. V/sub th/ should be kept around 0.3-0.4 V from an area size viewpoint. The minimum V/sub dd/ for SRAM operation is found to be 0.7 V in this study. It is also found that the supply voltage for SRAM cannot be scaled continuously.