2009 · 14 citations · 0 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignDevice ScalingIntegrated Circuit DesignLeakage Power ReductionMemory DevicesMetal-oxide-semiconductor Field-effect TransistorsElectron Impact IonizationGate-induced Drain LeakageIonizationLeakage Current ReductionLow-power Memory CircuitsMemory Circuit DesignNon-volatile Memory DesignSilicon
A Capacitorless IT-DRAM cell using gate-induced drain leakage (GIDL) current for write operation was demonstrated for the first time on FDSOI substrate, 9.5 nm silicon film and 19 nm BOX. 20 nm gate scaling improves 20% memory effect amplitude. GIDL mechanism allows low bias, low power, fast write time and does not affect intrinsic retention time. A similar value of 10 ms at 85degC is obtained like for impact ionization (II) optimised devices.