Evaluation of the Conventional vs. Ancient Computation Methodology for Energy Efficient Arithmetic Architecture

Abstract

VLSI design techniques are the key to re-engineering the digital gadgets of any kind which are needed to be operated with lower power to ensure a longer backup time. Power reduction in Arithmetic Logic Unit (ALU) is needed for this requirement. Multipliers and adders are the most important structures which use a larger fraction of power in such arithmetic units. This paper analyses the use of an ancient (or Vedic) mathematical approach for building an ALU. Validation for the low power operation of the circuit is made by designing a conventional CMOS counterpart whose power is compared with our ancient arithmetic design. A 4x4 multiplier based on the Vedic and Conventional methods have been designed using SPICE simulator. Simulation results depict the Vedic design incurring 29% of reduced average power.