V. S. Kanchana Bhaaskaran

Arbiter PUF—A Review of Design, Composition, and Security Aspects

S Hemavathy, V. S. Kanchana Bhaaskaran · IEEE Access · 2023 · 61 citations · Full text

Hardware Trojan, Engineering, Hardware Security Modules +17

A novel low power and high speed Wallace tree multiplier for RISC processor

C. Vinoth, V. S. Kanchana Bhaaskaran, B. Brindha et al. · 2011 · 41 citations

Engineering, Vlsi Design, Multiplier Architecture +19

Differential Cascode Adiabatic Logic Structure for Low Power

V. S. Kanchana Bhaaskaran, J. P. Raina · Journal of Low Power Electronics · 2008 · 32 citations

Low-power Electronics, Low Power, Electrical Engineering +14

Energy recovery performance of quasi-adiabatic circuits using lower technology nodes

V. S. Kanchana Bhaaskaran · India International Conference on Power Electronics 2010 (IICPE2010) · 2011 · 31 citations

Engineering, Energy Recovery Performance, Energy Efficiency +16

Implementation of Convolutional encoder and Viterbi decoder using Verilog HDL

V. Kavinilavu, S. Salivahanan, V. S. Kanchana Bhaaskaran et al. · 2011 · 29 citations

Maximum Likelihood Detection, Engineering, Forward Error Correction +10