On the design robustness of threshold logic gates using multi-input floating gate MOS transistors

Abstract

In this paper, the design robustness of logic circuits implemented as threshold logic gates with multi-input floating gate transistors is analyzed. The parameter variations of the basic components, namely the coupling capacitances of the floating gate MOSFETs and the sensing circuits for obtaining full logic levels, are investigated separately using appropriate array test structures. It is found that the dominant mismatch originates from the input offset voltage variations of the sensing circuits. Methods are presented for estimating the yield of a given logic circuit from the measured parameter distributions. The estimations are verified with measured data of a multiplier cell and of the encoding logic in a parallel fingerprint sensor architecture. Considerations are given for robust design of circuits based on threshold logic gates that use floating gate transistors.